First off, this class is not with the professor listed - you will spend the entirety of it with an assigned TA. Also, you will spend the entirety of it with a partner/group that you will choose at the first lab section, so if you want to minimize the risk of being paired with a useless partner, I recommend you sign up for this class with a friend. In this class, you will be learning Verilog and implementing some designs on an FPGA (circuit board) in Verilog. It's a pretty cool class I thought, as you get to get hands-on experience and see what computers are capable of even at a low level, but it's knowledge that won't really be too useful if you're going the software engineering route. In terms of workload, my partner and I handled pretty much all of our workload in class in terms of getting the code done, however there are open lab hours which we used maybe once or twice to be sure we would finish an assignment on time (you need to be physically present with the FPGA for testing, so can't do any testing on your own machine). Apart from that, there are lab reports that you need to do, but these usually would not take more than 2-3 hours per report, and there were only 4 or 5 of them throughout the entirety of the quarter.

Somehow they still don't get rid of this class yet. I couldn't contribute much to my team because the instructions were always unclear and I didn't even know where to start every lab. I was lucky enough to have a smart partner who literally carried the whole team but I ended up finishing this class learning nothing. We spent hours outside of class to develop the final project and it was exhasting. Hope I don't have to see Verilog again even though I'm a CSE major.

My TA for this class was Weitong Zhang. He did a good job lecturing and going over the project specs.
The class consisted of four projects. Before each project, the TA would give a lecture going over the spec, and the rest of the sections were just office hours. The projects primarily consisted of manipulating clocks and building FSMs using Verilog. It wasn't too difficult, and mainly built off of concepts from CS M51A/ECE M16. The projects were due every 2-3 weeks, which is more than enough time to complete them.

Ok so this class was with a TA, and I had Weitong Zhang, who was very friendly and helpful. The class is honestly pretty easy: there is 1-2 lectures about the next project, then the rest of the sections are OH until the project is due. It was relaxed.

There are 4 labs. The labs got a little hard at the end, but mostly if you pay attention to the pre-lab and use good practice for clocking, then you're A-OK.
The "code" is all done in Verilog, which is actually a description language (like HTML is to webpages): it describes digital systems, but doesn't "code" more than define behavior on certain signals. I say this bc it's a little hard to grasp at first, but easy once you get the hang of it. I did all the projects in <15 hours. If you design your module correctly, write good test cases, and make a lab report with all the right components, you get an A.

I'm not gonna lie, I wasn't a huge fan of Verilog before taking this class, and I still am not a fan of it. But the lab itself wasn't super hard. There were four projects, each of which required a lab report and a 10-minute video explanation of your Verilog code. I ended up grinding out most of them the weekend they were due (projects were due every other Sunday night), and I got pretty good grades, to say the least. My TA was also a nice guy who explained concepts well and graded the projects leniently. Overall, taking this class in COVID was a bit boring since we didn't get to work with actual hardware, but it wasn't a tough class by any means.

The assignments in this class take almost as long as a 4-unit course. We had 4 assignments, each requiring a 10-ish page report and a 10-minute video with your narration of your implementation. Good thing was that the grading was rather lenient and my TA was very clear and helpful in discussions. There is no Piazza/forum (CCLE forum was barely ever monitored) so you have to get started early and questions need to be asked in person. Overall not a bad class if you understood the gist of M51A. Projects are essentially the Verilog version of things we learned in M51A, not many new concepts.

From what I can tell compared to previous iterations of this class prior to this quarter, the class was made better. We did not have to deal with any FPGAs or anything so we did not have to go into any labs at any specific time because of the virus. We simply had to install a VM to run the software, or install it on a windows computer. Rather than having a group of 3 with 3 labs and 1 big final project, we had 5 individual labs. I prefer this because the labs were made more manageable and we did not have to make our own final project and I did not have to rely on other group members. It doesn’t matter who your TA is because each TA is responsible for grading each lab for all students. One TA would grade lab 1, another would grade lab 2, etc.

Grading:
10% Attendance/quizzes
15% Project 1
15% Project 2
20% Project 3
20% Project 4
20% Project 5

In the first few weeks, we did not have to show up to lecture and instead had to take easy quizzes to check that you watched the video recording or attended lecture. These were done on your own time and were easy. Midway through the quarter, in lieu of quizzes, they made attendance mandatory for project introductions. I got full credit on all this. Lab 1, I got 99% because I got marked off for some minor unspecified video error. For lab 2, I got 100%. Lab 3, I got 95% because I forgot to explain the synthesis report and summary. Lab 4 and 5 were a bit longer to finish and involved Finite state machines, but I also got 100% on both these. Lab 1 was 1 week, lab 2 was 2 weeks, lab 3 was 1 week, and the last two labs were each 2 weeks. The classes where they don’t introduce projects are essentially like office hours to ask questions about the project. You sign up for a slot beforehand with your TA.

Labs took me about 10-16 hours each. Reports were often long and time consuming. Some of my reports were 15-100 pages long, but most of it was just copy and pasting the synthesis and map reports which were long. But the contents of the reports are not trivial. It often took me about 6 hours for each lab report after finishing each project. Grading seemed fair as long as the projects worked and you put everything they asked for. Labs usually had median grades of high 80s or low 90s I think. With the exception of lab 2 which had a median of around high 70s since it was auto graded.

Some of the lab specs are a bit vague and people would ask for clarifications, so they often update the specs a lot.

At the end of the quarter, the professor emailed the whole class before the P/NP deadline to let us know he wasn’t going to down curve the class as opposed to in quarters because of the circumstances that happened in the world this quarter. Overall, we don’t interact with the professor other than if you email him or ask him for an office hours appointment.

Be very careful with the projects in this class. Do not make dumb mistakes. Follow the formatting directions exactly. A lot of people including myself messed up with these directions and did very poorly on some of the projects for that reason alone. Beyond that, this class isn't necessarily difficult, but it is a ton of work. The projects take at least a decent amount of time to code, but what takes the longest is writing test cases and writing reports. Those take numerous hours often times to write. For me at least my reports usually exceeded 20 pages. The specifications for the projects are very ambiguous so you need to make assumptions about how your project should behave. I didn't really think this class was that useful, but I wouldn't call it too hard either. It is just insanely time consuming. This quarter we got very lucky as Majid decided not to curve down. I don't know if I would have passed this class if he had curved down (I ended up with an 86% took it P/NP because we didn't know about the no curving down until later and I was scared I would make other mistakes dropping my grade even lower). Most people I knew got in the 90s despite the strict rules about formatting. So make sure to be on top of your work otherwise you can lose a lot of points and end up on the wrong side of the curve assuming majid will curve down in the future. From what he told us, not curving down is an exception rather than the norm.

Note: Class taken remotely during COVID-19.
tl;dr: this class is A LOT OF WORK for just 2 units. esp remotely. last few projects were difficult and we had to submit long reports AND record videos for each project. grading wasn't particularly harsh though.
This is the first time in a while where Sarrafzadeh is in charge of this course. However, you will not see the prof at all aside from OH. The TAs are in charge of your course. Honestly the TA does not matter too much as projects are all graded by the same TA for all students regardless of TA section.
I only attended my section for the first two weeks and did not go to any of the rest of the TA sections. I didn't find the sections very helpful and find learning on my own, i.e. googling, for the projects was faster.
There were in total 5 projects all in Verilog. All done individually(which kinda sucks). You have to download the Xilinx ISE in some form and I strongly recommend just dualbooting linux instead of using a virtual box which takes a lot of memory and is quite slow. First three projects weren't too difficult, but last two projects were VERY TIME CONSUMING. They're not incredibly hard, it just takes time to understand the vague specs, generate 100000(im exaggerating but you get the point) testcases, screen shot all the waveforms, write the long report, record the video...
Each project took me approximately a day(writing report+video generally took me around 3+ hours). It is quite a lot of effort for a 2 unit class.
The TAs aren't particularly harsh on the grading, but just make sure you follow the instructions carefully. Missing an explanation could cause you 5+ points out of 100.

Did I learn a lot about Verilog from this class? YES.
Was it worth the time? I am not sure.

This is a review of the M152A class, which he's in charge of but the TA's run. As all labs, your experience mainly depends on your TA. I got a pretty good TA. His exams and grading policy were all very fair. While the concepts themselves aren't that difficult (as long as you kind of get what happened in M51, you should be find). However, the major difficulty is the shoddy equipment + software you have to work with. It takes FOREVER to compile (you spend most of your lab time staring at the screen waiting for it to compile). Also - the software and/or transfer from the program to the hardware is buggy. Sometimes you can code/design it correctly, and have the waveform test show correct results, but the FPGA doesn't work somehow so you'll have to redesign it so some bug in the system will work. This is incredibly problematic for projects that require that the timer we build is accurate. Mainly we had a TA who understood this and wasn't incredibly stringent on a little deviation.